1. Field of the Invention
This invention relates to processors and, more particularly, to floating-point operations.
2. Description of the Related Art
In floating-point processing systems that perform multiply-accumulate operations (e.g., a multiply-add) such as A*C+B, where A, B, and C are floating-point numbers, rounding may generally be accomplished utilizing one of two techniques. The first technique may be referred to as “fused” multiply-add rounding, while the second technique may be referred to as “unfused” multiply-add rounding.
In a fused multiply-add, no rounding is performed between the multiplication operation and the subsequent addition/subtraction operation because the two operations are treated as one (fused) operation. Therefore, at most one rounding step occurs. In contrast, in the unfused case, the multiply-add operations may be treated as independent multiply and subsequent add/subtract operations with rounding being performed according to IEEE Std. 754-1985 after each of the two separate operations.
Because the multiply and add/subtract operations are treated independently in the unfused technique, it is possible for the multiply operation to cause an invalid operation, overflow, underflow, or inexact accrued exception to occur, and the corresponding current exception bits may be cleared by a subsequent add/subtract operation. Thus, the accrued exception bits within the floating-point state register, may not reflect the occurrence of the multiply operation exception if the accrued exception bits are obtained by simply OR-ing the present accrued exception bit value with the corresponding current exception bit value.